The present invention relates, in general, to electronics, and more particularly, to methods of forming semiconductors.
In the past, the semiconductor industry utilized various methods and equipment to singulate individual semiconductor die from a semiconductor wafer on which the die was manufactured. Typically, a technique called scribing or dicing was used to either partially or fully cut through the wafer with a diamond cutting wheel along scribe grids that were formed on the wafer between the individual die. To allow for the alignment and the width of the dicing wheel each scribe grid usually had a large width, generally about one hundred fifty (150) microns, which consumed a large portion of the semiconductor wafer. Additionally, the time required to scribe all of the scribe grids on the entire semiconductor wafer could take over one hour or more. This time reduced the throughput and manufacturing capacity of a manufacturing area.
Other methods have been explored as alternatives to scribing, which have included thermal laser separation (TLS), stealth dicing (laser dicing from the backside of the wafer), and plasma dicing. However, the other methods have had several manufacturing challenges, which have included uncontrollable crack propagation, non-compatibility with backmetal layers, added passivation layers, limitations on die size reduction, and degraded device electrical characteristics.
Accordingly, it is desirable to have a method of singulating die from a semiconductor wafer that is controllable, that is compatible with wafers having backmetal, that can be used to separate smaller semiconductor die, that provides more uniform and reliable singulation, that reduces the time to perform the singulation, and that has a narrower scribe line. Also, it would be advantageous if the method is compatible with wafers having backside coating materials (WBC).
For simplicity and clarity of the illustration, elements in the figures are not necessarily to scale, and the same reference numbers in different figures denote the same elements. Additionally, descriptions and details of well-known steps and elements are omitted for simplicity of the description. For clarity of the drawings, doped regions of device structures may be illustrated as having generally straight line edges and precise angular corners. However, those skilled in the art understand that due to the diffusion and activation of dopants the edges of doped regions generally may not be straight lines and the corners may not be precise angles. Furthermore, the term “major surface” when used in conjunction with a semiconductor region, wafer, or substrate means the surface of the semiconductor region, wafer, or substrate that forms an interface with another material, such as a dielectric, an insulator, a conductor, or a polycrystalline semiconductor. The major surface can have a topography that changes in the x, y and z directions.